(a) Field of the Invention
The present invention relates to semiconductor memory devices including electrically programmable nonvolatile memory cells. In particular, the present invention relates to semiconductor memory devices adapted for a test method for checking the nonvolatile memory cells for failure using a burn-in process.
(b) Description of Related Art
Conventionally, as semiconductor memory devices in which data is stored in elements integrated on a semiconductor substrate, nonvolatile semiconductor memory devices are used which can retain data even when power is not supplied. Particularly, flash EEPROMs capable of electrically writing and erasing data are commonly used which have a floating gate electrode with the surrounding thereof insulated by an oxide film or the like and a control gate electrode formed above the floating gate electrode with a capacitor insulating film interposed therebetween.
(First Conventional Example)
FIG. 17 shows the block configuration of a flash EEPROM according to a first conventional example. As shown in FIG. 17, the flash EEPROM of the first conventional example is provided with a memory cell array 101 in which memory cells MC11 to MCmn are arranged in matrix. The flash EEPROM is further provided with, as peripheral circuits for driving the memory cell array 101, a word line driver 102 for driving word lines WL1 to WLm, a bit line driver 103 for driving bit lines BL1 to BLn, and a source line driver 104 for driving a source line SL.
Each of the memory cells MC11 to MCmn includes a floating gate electrode, a control gate electrode, and two doped regions. The floating gate electrode is formed above a semiconductor substrate with a tunnel insulating film interposed therebetween. The control gate electrode is formed above the floating gate electrode with a capacitor insulating film interposed therebetween. The two doped regions are formed to interpose a portion of the semiconductor substrate located below the floating gate electrode, and they serve as a source electrode and a drain electrode.
As the tunnel insulating film, use is made of a silicon oxide film with few crystal defects formed by thermal oxidation. As the capacitor insulating film, use is made of an ONO film formed by sequentially stacking a first silicon oxide film, a silicon nitride film, and a second silicon oxide film.
The flash EEPROM of the first conventional example stores, as data, electric charges accumulated in the floating gate electrodes of the memory cells MC11 to MCmn.
The flash EEPROM of the first conventional example performs writing operation on, for example, the memory cell MC11 in the following manner. The word line driver 102 and the bit line driver 103 select a memory cell to be targeted for writing operation, and the drivers apply control voltages of, for example, about 5 V to the word line WL11 and the bit line BL11, respectively. Thus, charges in the source electrode are injected through the tunnel insulating film into the floating gate electrode.
The flash EEPROM performs reading operation on the memory cell MC11 in the following manner. The bit line BL11 is precharged and a control voltage of, for example, about 2.5 V is applied to the word line WL11. The threshold of the control gate voltage at which current starts to flow in a channel region differs according to the amount of charges stored in the floating gate electrode. If the threshold voltage of the memory cell MC11 is lower than the voltage applied to the control gate electrode, the direction of the potential of the bit line BL11 is changed to the positive direction. On the contrary, if the threshold voltage thereof is higher than the voltage applied to the control gate electrode, the direction of the potential of the bit line BL11 is changed to the negative direction.
The flash EEPROM performs erasing operation on the memory cell MC11 in the following manner. A control voltage of, for example, about −5 V is applied to the word line WL11 and a control voltage of about 5 V is applied to the source line SL. Thus, erasing operation is performed at a time on all the memory cells MC11 to MC1n, connected to the word line WL11.
In writing operation or reading operation of a nonvolatile semiconductor memory device including memory cells, the same control voltage is applied not only to memory cell targeted for the operation but also to memory cells connected to the common word line or the common bit line with the target memory cell. By this control voltage, charges accumulated in the floating gate electrode may leak (may be disturbed) through the capacitor insulating film or the tunnel insulating film to the semiconductor substrate side or the control gate electrode side, and then data in the device might be corrupted.
To prevent such a possible problem and ensure the reliability of the flash EEPROM, a disturb test is conducted for checking whether the memory cells can store data with reliability for a predetermined period of time and screening early failures in the EEPROM.
The disturb test includes the process (burn-in process) in which using a burn-in apparatus, a voltage acting as a stress is applied to word lines or bit lines for a predetermined period of time and the process in which data stored in the memory cell is checked for corruption by the stress application.
Specifically, in advance, a prescribed data is written in a memory cell array in a flash EEPROM. First, the EEPROM is connected to a burn-in apparatus. A voltage as a stress supplied from the burn-in apparatus is applied to all the word lines WL1 to WLm or all the bit lines BL1 to BLn for a predetermined period of time. Although not shown, the flash EEPROM of the first conventional example is provided with a burn-in test circuit as a circuit for controlling the stress application process (burn-in process) with the burn-in apparatus, and operations of the word line driver 103 and the bit line driver 104 are controlled based on the control signal from the burn-in apparatus.
Subsequently, data in the memory cell is read out with a tester or the like, and the data is checked for variation caused during the stress application. If the stress application varies the data in the memory cell, the memory cell is judged to be failure.
If the word line driver 103 or the bit line driver 104 in the flash EEPROM of the first conventional example has early failure, however, a stress as predetermined may not be applied in the burn-in process described above. In this case, because of an inadequate stress application, even a memory cell with a low disturb property is erroneously judged to be normal.
(Second Conventional Example)
To prevent such a misjudgment, in a second conventional example, a means for determining whether or not a predetermined voltage is applied to the word lines and the bit lines is provided.
For example, Japanese Unexamined Patent Publication No. 10-302498 discloses an EPROM in which a circuit for measuring a bit line potential is provided as a means for detecting whether or not a predetermined voltage is applied to bit lines in a writing test. In the second conventional example, a circuit similar to the bit-line-potential measurement circuit described in this publication is provided, thereby enabling measurement of a bit line potential and a word line potential.
FIG. 18 is a block diagram showing how to conduct a disturb test on a flash EEPROM of the second conventional example. As shown in FIG. 18, in a flash EEPROM 110 of the second conventional example, a word line driver 102 and a bit line driver 103 are controlled by a burn-in test circuit 111 which receives a control signal and a stress voltage from a burn-in apparatus 200 to control a burn-in process.
The flash EEPROM 110 is connected through a burn-in board (not shown) to the burn-in apparatus 200. A plurality of flash EEPROMs 110 are arranged on one burn-in board, and a plurality of burn-in boards are connected to the burn-in apparatus 200. Therefore, a stress is applied at a time to a number of flash EEPROMs 110.
When a stress is applied to the word lines WL1 to WLm, word line selection transistors WST1 to WSTm are sequentially turned on and a word-line-potential measurement circuit 112 sequentially measures voltages applied to the word lines WL1 to WLm. The result of each measurement is supplied to a selector circuit 114.
Likewise, when a stress is applied to the bit lines BL1 to BLn, bit line selection transistors BST1 to BSTn are sequentially turned on and a bit-line-potential measurement circuit 113 sequentially measures voltages applied to the bit lines BL1 to BLn. The result of each measurement is supplied to the selector circuit 114.
The selector circuit 114 selectively supplies to a comparator 201 the measurement results received from the word-line-potential measurement circuit 112 and the bit-line-potential measurement circuit 113. The comparator 201 determines whether or not the applied voltage is identical to the prescribed voltage. Based on the output from the comparator 201, the burn-in apparatus 200 adjusts a stress voltage to be applied to the word lines WL1 to WLm and the bit lines BL1 to BLn so that a voltage as prescribed is applied to the word lines WL1 to WLm and the bit lines BL1 to BLn. 
However, the second conventional example includes not only the word-line-potential measurement circuit 112 and the bit-line-potential measurement circuit 113 but also a signal line and a control circuit for separately controlling the bit line selection transistors BST1 to BSTn and the word line selection transistors WST1 to WSTm. Therefore, the chip area of the flash EEPROM extremely increases. Moreover, the burn-in apparatus 200 has to be provided with the comparators 201 equal in number to the EEPROMs to be tested at a time, so that costs necessary for the burn-in apparatus 200 increase as well.
As described above, the conventional flash EEPROM has the problem in which a reliable implementation of the disturb test results in increases in the chip cost and the test cost of the flash EEPROM.